シリコン基板上ヘテロエピタキシースレディング転位の発生と伝播制御(<小特集>格子不整合系のヘテロエピタキシー)

抄録

The practical application of GaAs on Si technology into combining optoelectronic and high-speed devices is our hopefully rewarding long-term objective. To achieve this, the defect density in GaAs on Si needs to be reduced to values obtainable in bulk or homoepitaxial GaAs (≦10^4/cm^2). We discuss in the present paper recent progress of GaAs on Si technology from the viewpoint of how to be able to suppress the threading dislocation density in GaAs layers on the basis of the results which were obtained throughout the course of investigation in OTL. In particular, the effects of new materials for buffer layers and insertion layers, doped-impurities, growth area confinement, substrate orientation and high-temperature annealing on the reduction of threading dislocation generation and propagation, are described. These results are discussed by considering two groups of misfit dislocations at the interface regions between GaAs and Si.