1995 年 10 巻 5 号 p. 720-730
For verification, synthesis and design of hardware systems, various formal specification languages have been used in a combined form, which are temporal logics, finite state machine languages, data flow graphs and hardware description languages. Furthermore, informal natural language expressions are supplemented for the unified descriptions of time, action, state transition and causality, and for the abstract descriptions such as functions and hierarchy of devices. This paper proposes a method for situational and dynamic interpretation of natural language descriptions as well as formal language ones in hardware design specifications. Natural language expressions are formulated by the multi-modal predicate logic integrating logics of time, action, causality, conditional and knowledge. The semantics of the logic is given by first-order logic formalization based on verification-conditional and situational semantics. The satisfiability of logical formulas is defined by the provability in a situation description, which consists of first-order logical formulas representing factual situations, constraints and general rules in hardware systems. This paper presents the methods for transformation of natural language expressions into the first-order logical formulas through the multi-modal logical ones, and for description of the rules on modality, device action, register transfer and control state transition by the first-order logic. An efficient method for dynamic interpretation using belief revision is given which is based on the inference mechanism of the first-order logic and is reinforced with default reasoning and meta-level reasoning. The above processing system is implemented by Prolog language.
