2022 Volume 22 Issue 2 Pages 91-95
This paper explains die attach optimization technologies for silicon carbide (SiC) device packaging. High power density power module products are achieved by utilizing silicon carbide (SiC) chip owing to its excellent device properties with high temperature durability, low power conversion loss energy. Toward SiC chip packaging, new die attach technique bonded with high thermal conductivity substrate is required to remove high thermal flux generated around the small sized SiC chip. Especially, sintered silver (s-Ag) die bonding technique has attracted so many researchers owing to its high thermal conductivity, melting point, although low temperature bonding process condition. However, thermal shocked test (TST) has generally imposed as a practical operation reliability test that accompanies with thermal and mechanical stress degradation in the s-Ag die-attach area. After TST, die area shrinks, which makes thermal impedance worse compared to the initial state. Therefore, not only bonding s-Ag but also taking into material stress durability. s-Ag bonded with copper (Cu) substrate with 1mm, 2mm thick assemblies were performed through TST with -40 to 150℃ up to 1000 cycles. Die degradation evaluation was utilized by scanning acoustic tomography (SAT) images.
