Timing Verification System for Relay Circuit Behaviors

抄録

A timing verification system for analogue relay circuits has been developed. The verification is performed by Time-Symbolic Logic (TSL) simulation that allows symbolic representation of the time. With representation of the relay actuation time by time-variables, TSL simulation can simulate all possible behaviors that differ with the timing of relay action. To reduce the simulation cost, the simulation technique was improved using the characteristics of the relay circuits. Users can verify the circuit behavior without preparing numerous simulation inputs or executing numerous simulation cases.
The developed system was applied to the verification of actual circuits. The circuit behaviors with all the possible timings under the realistic constraints were simulated and verified. These application studies confirmed that the developed system is useful and effective.