Optimizing a Field-Programmable Gate Array Object Detection System Considering Processing System and Programmable Logic Load Balance

Abstract

A field-programmable gate array (FPGA) device with a Zynq architecture integrates a processing system (PS) and programmable logic (PL) into a single chip. Although the PL performance is typically considered, the PS load cannot be completely ignored. In this study, using an FPGA board with a Zynq architecture, the conditions under which an object detection system performs the best, while considering the PS and PL load balance, are explored.