抄録
This paper presents the residual and transient thermal stresses in a laminate board in which passive and active elements are embedded. The residual stress is generated because of mismatch of thermal expansion. The residual stress concentration is observed in the wiring layers between the silicon chips as well as near the interfaces between different constituent materials. Transient thermal stress due to heat generation in the silicon ships relaxes the initial residual stress when an appropriate heat sink is employed for cooling down the board. The classical lamination theory can approximately estimate the in-plane residual stress.
