抄録
Iterative stencil computation is one of typical computation patterns appearing in engineering and other research fields. When naively implementing a program of iterative stencil computation, its performance is usually limited by the memory bandwidth of a computer system. Temporal and spatial tiling is known as a technique for improving the performance of iterative stencil computation by reducing its memory access cost. In this paper, an overview of the temporal and spatial tiling techniques is presented, and its application to 3-dimesional FDTD method is reported.
