M&M材料力学カンファレンス
Online ISSN : 2424-2845
セッションID: GS07
会議情報
GS07 次世代半導体パッケージのシリコン貫通ビア中のボイド周りの応力状態
木下 貴博川上 崇島 俊平松本 圭司小原 さゆり折井 靖光
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会議録・要旨集 フリー

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抄録
Thermal stresses around void in TSV (Through Silicon Via) structure in 3D SiP were discussed under the conditions of device operation and reflow process by using ADVENTURECluster, which was a large scale simulator based on finite element method (FEM). In case of the condition of device operation, equivalent stress around void inside Cu TSV was estimated at around 100 MPa. It showed the low possibility for low cycle fatigue of Cu TSV under device operation because that the stress was lower than yield stress of copper, 230MPa. In case of the condition of reflow process, the equivalent stress of TSV and micro bump were higher than yield stress of Cu. However temperature elevation due to reflow process was once or twice during the process. It showed the low possibility for fracture by low cycle fatigue under reflow process. Stress concentrations were occurred at parts of corner and interface of materials. It has possibility that singular stress field was formed at the parts, and we should discuss fracture induced by singular stress field.
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© 2013 一般社団法人 日本機械学会
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