Abstract
Recently, Computational Fluid Dynamics is widely used in electronic equipment thermal design process. With regard to semiconductor packages in electronic equipment, two-resistor thermal models are usually available in order to reduce thermal simulation calculation time. However, it is known that two-resistor models include several kinds of calculation error. In this study, a calculation error reduction method for two-resistor thermal models is newly developed. Novel error reduction method applying to BGA packages consists of three steps to correct package thermal resistances measured by JEDEC method. Usually, more than 20% junction temperature rise error occurs in various cooling condition such as fan cooling and heat-sink cooling. In our study, it is clarified that less than 5% error of calculated temperature rise could be achieved in almost cooling conditions.
