パワー半導体デバイスのパッケージ熱抵抗に関する研究

上面及び底面の境界条件を変えた際の影響について

抄録

Adequate thermal management of power semiconductor devices is vital for downsizing and power saving of power electronics systems. However, in many cases, temperature prediction is conducted based on a specific boundary condition, which is different from one real system faces without considering its influence on temperature prediction result. This paper investigates package thermal resistance of DPAK package as one of important standard power semiconductor device packages to understand temperature prediction result difference by boundary conditions. Through investigation with the case that heat flows from top and bottom surface of the package, it is found that package thermal resistance varies by heat transfer coefficient value set to bottom surface.