Journal of Signal Processing
Online ISSN : 1880-1013
Print ISSN : 1342-6230
FPGA Implementation of Single-Image Super-Resolution Based on Frame-Bufferless Box Filtering
Yuki SanadaTakanori OhiraSatoshi ChikudaMasaki IgarashiMasayuki IkebeTetsuya AsaiMasato Motomura
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2013 Volume 17 Issue 4 Pages 111-114

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Abstract

Recently, a novel algorithm of filter-based single-image super-resolution (SR) has been proposed. We here propose a hardware-oriented image-enlargement algorithm for the SR algorithm based on frame-bufferless box filtering, and present novel circuits of the proposed enlargement algorithm and the SR algorithm for an field-programmable gate array (FPGA), aiming at the development of single-image SR module for practical embedded systems.

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© 2013 Research Institute of Signal Processing, Japan
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