抄録
In many nonlinear applications, hardware architectures for the particle swarm optimization (PSO) algorithm are implemented to obtain the optimum solution. However, the conventional hardware implementation is inefficient when the arithmetic equations in the application become complex. To overcome this problem, this paper presents a two-level pipeline structure for the PSO algorithm based on field-programmable gate array (FPGA) technology. The proposed hardware employs two novel features. First, a generic particle calculation block (GPCB) is adopted to support different kinds of PSO algorithm. Second, a twolevel pipeline approach is adopted, which helps to increase the calculation speed of the proposed hardware. The experimental results demonstrate that the proposed architecture achieves higher performance than conventional hardware.
