A 1-Msps 500-Node FORCE Learning Accelerator for Reservoir Computing

抄録

A major issue in the conventional First-Order Reduced and Controlled Error (FORCE) learning architecture is the low processing speed due to extensive matrix-vector calculations for learning. In this study, we present the field programmable gate array architecture of FORCE learning that achieves the processing of 1-Msps 500-Node data. As a result, the learning was accomplished approximately 3,400 times faster while maintaining the original accuracy in a simulation under specified conditions.