FPGA Implementation of a Multi-Threshold Delay-Based Physically Unclonable Function with a Time-to-Digital Converter

Abstract

Physically Unclonable Functions (PUFs) are security primitives designed to generate chip-specific responses by exploiting inherent device variations that are difficult to reproduce. One approach to implementing a PUF is known as Response Generation according to Delay Time Measurement (RG-DTM), which measures the delay time difference between two paths using a multi-offset sense amplifier. However, implementing the RG-DTM PUF on a Field-Programmable Gate Array (FPGA) is impractical, as the sense amplifier is an analog circuit. To address this limitation, the fDTM-PUF has been proposed, which uses multiple D flip-flops (DFFs) to measure the delay time differences. Despite this improvement, implementing the fDTM-PUF on an FPGA remains challenging due to the strict layout constraints of FPGAs. In this paper, we propose the fTDC-PUF, which measures the delay time difference using a Time-to-Digital Converter (TDC) sensor. The fTDC-PUF is more easily implemented on FPGAs and allows for finer delay time measurements compared to conventional methods. This paper evaluates the fundamental characteristics of the fTDC-PUF, including uniqueness and steadiness, under various settings.