Plasma Etch Challenges for Nanoscale ULSI Device Fabrication: Modeling and Simulation of Surface Roughening and Rippling during Plasma Etching of Si

Abstract

Atomic- or nanometer-scale surface roughness has become an issue to be resolved in the fabrication of nanoscale ULSI devices, because the roughness at feature sidewalls and bottom surfaces is responsible for the variability in transistor performance. This paper presents a numerical and experimental study of surface roughening during plasma etching of Si in Cl₂, with emphasis being placed on modeling, analysis, and control of plasma-surface interactions concerned. A three-dimensional atomic-scale cellular model (ASCeM-3D) based on Monte Carlo (MC) algorithm exhibited nanoscale surface roughening and rippling in response to ion incidence angle onto surfaces. Experiments were conducted to demonstrate the validity of our ASCeM-3D model, and to investigate how to suppress and/or control the formation of surface roughness and ripples during plasma etching, where a classical molecular dynamic (MD) simulation for Si/Cl and Si/SiCl systems was also invoked to further understand atomistic mechanisms concerned.