Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLKT.M./SiO2 Hybrid Structure

Masanobu Ikeda; Kenichi Watanabe; Yoshiyuki Kotani; Michiari Kawano; Hiroko Mori; Takahiro Kimura; Takashi Suzuki; Noriyoshi Shimizu; Tomoji Nakamura; Iwao Sugiura; Ei Yano; Kiyotaka Tabuchi; Toshiaki Hasegawa; Shingo Kadomura

doi:10.2320/matertrans.43.1577

Integration of High Performance CMOS Logic LSI by Applying Cu Wiring to SiLK^T.M./SiO₂ Hybrid Structure

Masanobu Ikeda, Kenichi Watanabe, Yoshiyuki Kotani, Michiari Kawano, Hiroko Mori, Takahiro Kimura, Takashi Suzuki, Noriyoshi Shimizu, Tomoji Nakamura, Iwao Sugiura, Ei Yano, Kiyotaka Tabuchi, Toshiaki Hasegawa, Shingo Kadomura

著者情報

Masanobu Ikeda
Manufacturing Technology Development Division, Electronic Device Group, FUJITSU Limited
Kenichi Watanabe
Manufacturing Technology Development Division, Electronic Device Group, FUJITSU Limited
Yoshiyuki Kotani
Manufacturing Technology Development Division, Electronic Device Group, FUJITSU Limited
Michiari Kawano
Manufacturing Technology Development Division, Electronic Device Group, FUJITSU Limited
Hiroko Mori
LSI Quality Assurance Division, Electronic Device Group, FUJITSU Limited
Takahiro Kimura
Device Fabrication Analysis Laboratory, FUJITSU Laboratories Limited
Takashi Suzuki
LSI Materials Development Department, C Project, FUJITSU Laboratories Limited
Noriyoshi Shimizu
LSI Materials Development Department, C Project, FUJITSU Laboratories Limited
Tomoji Nakamura
LSI Materials Development Department, C Project, FUJITSU Laboratories Limited
Iwao Sugiura
Inorganic Materials and Polymer Laboratory, FUJITSU Laboratories Limited
Ei Yano
Inorganic Materials and Polymer Laboratory, FUJITSU Laboratories Limited
Kiyotaka Tabuchi
LSI Technology Development Division, Semiconductor Network Company, SONY Corporation
Toshiaki Hasegawa
LSI Technology Development Division, Semiconductor Network Company, SONY Corporation
Shingo Kadomura
LSI Technology Development Division, Semiconductor Network Company, SONY Corporation

キーワード: copper wiring, low-k material, SiLK^T.M./SiO₂ hybrid structure, adhesion, dual damascene, static random access memory, electromigration

ジャーナルフリー

2002 年 43 巻 7 号 p. 1577-1584

DOI https://doi.org/10.2320/matertrans.43.1577

詳細

抄録

This paper describes a 0.13-\\micron CMOS made by using highly reliable copper and SiLK^T.M. (DOW CHEMICAL) interconnection technologies. We propose a hybrid interlayer structure with SiLK^T.M. at the trench level and SiO₂ at the via level to improve electrical properties, mechanical strength, and reliability. Using these technologies, we made a fully functional 1.5-Mbit SRAM macro and investigated the reliability of its copper wiring in terms of electromigration.

責任著者(Corresponding author)

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