[Paper] FPGA-based Performance Evaluation of FEC Codes for an Advanced ISDB-T

抄録

We are developing an advanced Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) system for the next generation of digital terrestrial television broadcasting. The advanced ISDB-T provides 4K8K terrestrial broadcasting service for fixed reception and 2K service for mobile reception simultaneously within one channel. New technologies such as Low-Density Parity-Check (LDPC) code are used for expanding the transmission capacity and for improving the spectral efficiency. The LDPC codes designed for the advanced ISDB-T have two code lengths and 13 code rates for each code length. The code length and code rate can be selected in consideration of the transmission latency requirement or the link budget. Meanwhile, although the LDPC codes have good bit error rate (BER) performance approaching the Shannon limit, a small number of error bits cause an error floor even if the E_s/N₀ is high enough. The error floor may cause serious issues such as block noise in video and mute in audio because broadcasting is a real-time service without any feedback. To deal with this problem, Bose-Chaudhuri-Hocquenghem (BCH) code is concatenated as outer code to the LDPC codes as inner codes. We conducted a simulation using a field programmable gate array (FPGA) instead of a computer to evaluate the BER performance. An FGPA simulation is 1000 times faster than a computer simulation, so the BER performance can be evaluated quickly with an adequate number of measurement bits. As a result, it was confirmed that LDPC codes perform as designed both in the water-fall and error-floor regions and that the BCH codes correct the small number of error bits after the LDPC decoder.