Design of load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances

抄録

This paper presents a numerical design approach of the load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances. The design curves of the load-independent class-E inverter are also given. A design example is shown along with its LTspice simulation and laboratory experiment. By applying the proposed design approach, there are no changes in the output-voltage waveforms and all the switch-voltage waveforms satisfy the zero-voltage-switching (ZVS) condition even the load-resistance value varies from the desired one without applying any tuning processes. Additionally, the results obtained from the LTspice simulation and laboratory experiment show quantitative agreement with the numerical predictions, which shows the effectiveness of the proposed design approach and design curves of the load-independent class-E inverter with MOSFET gate-to-drain and drain-to-source parasitic capacitances given in this paper.