Smart hardware architecture with random weight elimination and weight balancing algorithms

抄録

Reducing the number of connections in hardware artificial neural networks, as compared with their software counterparts, can result in a drastic reduction in costs, because the reduction translates into utilizing fewer devices. This paper presents the demonstration of a method, by using simulations, to halve the amount of weights in a network while minimizing the accuracy loss. Additionally, the appropriate considerations for translating these simulation results to hardware networks are also detailed.