C-element-based latch with DNU tolerance and SET resilience around clock edges

抄録

Technology scaling and supply-voltage reduction increase the susceptibility of sequential circuits to radiation-induced soft errors. In particular, double-node upsets (DNUs) in the hold state and single-event transients (SETs) around clock transitions have emerged as major reliability concerns in nanoscale technologies. This work investigates two C-element-based latch (CEBLT) variants, CEBLT-1 and CEBLT-2, to improve robustness against both disturbance types. HSPICE simulations in a 15 nm FinFET process show that CEBLT-1 tolerates 60.0% of all possible DNU combinations, while the remaining failures are primarily caused by reverse propagation at the output stage. To mitigate this limitation, an enhanced latch structure, CEBLT-2, is introduced. The results demonstrate that the DNU tolerance coverage is increased to 88.9%, and further to 97.8% when CEBLT-2 is employed as the master stage of a master–slave flip-flop. Both latch designs also exhibit strong tolerance to input-node SETs around clock transitions. Compared with existing DNU-tolerant latch designs, the proposed latch family addresses hold-state DNU tolerance and clock-edge SET resilience within a unified architecture, while maintaining competitive area, delay, and power characteristics. These results indicate that C-element-based latch structures can be systematically enhanced to achieve improved soft-error robustness in advanced sequential circuits.