抄録
This paper presents a novel application of an operational transconductance amplifier configuration for implementing the basic logic gates using the concept of stochastic resonance (SR). In such framework, the SR effect applied to nonlinear electrical systems to build logical gates (SR gates) has been studied. The property of hysteresis is crucial: first, it reduces the error rate regarding mismatch problems with cooperative use of noise, and second, it ensures the stability of all logic states. However, in this configuration, the toggles exhibit an unpredictable delay, which has been reviewed in this study; therefore, the most suitable application of the SR gates is in asynchronous circuit design. Circuit performance was electrically simulated using SPICE for 0.18-µm CMOS technology. The simulation results have proven the effective performance of the SR gates for an optimal amount of noise working at low power consumption, despite the introduction of an intentional mismatch between the threshold voltages of the transistors.
