加速器
Online ISSN : 2436-1488
Print ISSN : 1349-3833
解説
デジタル低電力高周波系の開発
道園 真一郎 穴見 昌三片桐 広明方 志高松本 利広三浦 孝子矢野 喜治山口 誠哉小林 鉄也
著者情報
ジャーナル フリー

2008 年 5 巻 2 号 p. 127-136

詳細
抄録

One of the biggest advantages of the digital low level rf (LLRF) system is its flexibility. Owing to the recent rapid progress in digital devices (such as ADCs and DACs) and telecommunication devices (mixers and IQ modulators), digital LLRF system becomes popular in these 10 years. The J–PARC linac LLRF system adopted cPCI crates and FPGA based digital feedback system. Since the LLRF control of the normal conducting cavities are more difficult than super conducting cavities due to its lower Q values, fast processing using the FPGA was the essential to the feedback control. After the successful operation of J–PARC linac LLRF system, we developed the STF (ILC test facility in KEK) LLRF system. Since the klystron drives eight cavities in STF phase 1, we modified the FPGA board. Basic configuration and the performances of these systems are summarized. The future R&D projects (ILC and ERL) is also described from the viewpoints of LLRF.

著者関連情報
© 2008 日本加速器学会
前の記事 次の記事
feedback
Top