Abstract

We developed carbon nanotube (CNT) vias and their low-temperature fabrication processes consisting of low-temperature CNT growth and chemical mechanical polishing (CMP) of the CNT bundles. We were able to lower the CNT growth temperature to 400°C, which meets the requirement to avoid thermal damage to LSIs. Not only was the CMP effective for planarization; it also lowered the via resistance with improved distribution. Our low-temperature CNT via technologies are very promising for the achievement of low-resistance CNT vias for future LSI interconnects.