Abstract
Self-alignment of MEMS or IC chips onto carrier wafer with high accuracy is one the most essential steps to size-free MEMS-IC integration. In our previous works, we have found that the chip diced by Deep-RIE exhibits preferred high alignment accuracy, while the chips diced by blade always suffers from miss-alignment. In this paper, to avoid expensive and time-consuming Deep-RIE process, high speed camera was applied to study the self-alignment phenomena when the chips were diced by Deep-RIE or blade. Based on above results, an improved chip-dicing approach was proposed by using Deep-RIE to precisely define the chip size and using FDTS-coating to improve hydrophobic properties of chip cross-section surface. High-speed (<0.08s) and high accurate self-alignment (<1μm) was therefore successfully achieved by using chips obtained by blade dicing.
