HARDWARE and SOFTWARE APPROACH for IDDQ TEST

Abstract

IDDQ test based on pattern selection has began for 0.6um and 0.5um CMOS gate array series. Current free structure has been introduced for all functional macro cells of these series. Precise IDD measurements are realized by current flow cut for pull-up and pull-down buffers using test pads at wafer level testing. IDDQ test using variable threshold, calculated by a CAD tool from circuit conditions, is applied to package level testing. This hardware and software combination achieves high defect coverage with no customer penalty.