We consider the system consisting of components located on some triangles. This system fails if and only if three components on a triangle fail. This system is called by an adjacent triangle : F triangular lattice system. Our purpose is to propose a useful method for the reliability of the adjacent triangle : F triangular lattice system. For our purpose, we consider a linear connected-(2,(1,2))-out-of-(m, n) : F lattice system. It is shown that the adjacent triangle : F triangular lattice system can be expressed as the linear connected-(2,(1,2))-out-of-(m, n) : F lattice system. We propose a useful method for the reliability of the linear connected-(2,(2,1))-out-of-(m, n) : F lattice system. Some numerical examples are shown.

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IDDQ test based on pattern selection has began for 0.6um and 0.5um CMOS gate array series. Current free structure has been introduced for all functional macro cells of these series. Precise IDD measurements are realized by current flow cut for pull-up and pull-down buffers using test pads at wafer level testing. IDDQ test using variable threshold, calculated by a CAD tool from circuit conditions, is applied to package level testing. This hardware and software combination achieves high defect coverage with no customer penalty.

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[in Japanese]

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