Abstract
The quiescent Vdd-GND current(I_<DDQ>) of a defect-free CMOS circuit is usually very small while a defective circuit often draws excessive I_<DDQ>. As a result, I_<DDQ> information is useful in testing and failure analysis of CMOS circuits. Moreover, it has been shown that the stuck-at fault model and logic testing can not cover some sefects in a CMOS circuit. Thus, I_<DDQ> information is also indispensable in performing high-quality testing and highly efficient failure analysis. This paper uses the transistor short fault model and describes the principle of I_<DDQ> testing, methods of selecting I_<DDQ> test vectors and ways of conducting fault diagnosis with both I_<DDQ> and logic information.
