The Journal of Reliability Engineering Association of Japan

Online ISSN : 2424-2543
Print ISSN : 0919-2697
ISSN-L : 0919-2697

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Volume 19, Issue 4

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[title in Japanese]

Article type: Cover
1997 Volume 19 Issue 4 Pages Cover1-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_Cover1

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[title in Japanese]

Article type: Index
1997 Volume 19 Issue 4 Pages i-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_i

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[title in Japanese]

Article type: Index
1997 Volume 19 Issue 4 Pages ii-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_ii

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[title in Japanese]

[in Japanese]

Article type: Article
1997 Volume 19 Issue 4 Pages 243-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_243

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Reliability of Sub 0.1um MOS Devices and Scaling Limitation

Mitumasa Koyanagi

Article type: Article
1997 Volume 19 Issue 4 Pages 244-256
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_244

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Problems and future trend in LSI multi-level interconnection reliability technology

Shosou Zingubara

Article type: Article
1997 Volume 19 Issue 4 Pages 257-263
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_257

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A model for the intrinsic breakdown in thin gate oxides

Takayuki Tomita, Hiroto Utunomiya, Kenzi Taniguchi, Yoshinari Kamakura

Article type: Article
1997 Volume 19 Issue 4 Pages 264-273
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_264

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Problems of soldering heat test methods for surface mount LSIs and their countermeasures

Masaki Tanaka

Article type: Article
1997 Volume 19 Issue 4 Pages 274-280
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_274

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Electromigration of Al-Cu at Tungsten Plug Contacts/Vias

Hisao Kawasaki

Article type: Article
1997 Volume 19 Issue 4 Pages 281-288
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_281

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Si Device Analysis Using Laser Beam Heating : Recent Topics On OBIRCH method

Kiyoshi Nikawa

Article type: Article
1997 Volume 19 Issue 4 Pages 289-299
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_289

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THE IMPACT OF IC DESIGN-FOR-TEST ON TIME-TO-MARKET

Terry R. Harms, Peter Maxwell

Article type: Article
1997 Volume 19 Issue 4 Pages 300-308
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_300

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In the changing VLSI test environment, this paper re-examines the VLSI Test development trade-off of quality, cost of Test development and Time-to-Market. The paper looks at what technology has been available in the recent past and is currently available to reduce Time-to-Market in terms of Design-for-Test, the types of Test, and automation possibilities. Finally it briefly looks at future opportunities for the contribution of VLSI Test to the reduction of Time-To-Market for a VLSI chip.

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Fault Detection and Fault Diagnosis with I_<DDQ> Measurement

Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita

Article type: Article
1997 Volume 19 Issue 4 Pages 309-317
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_309

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The quiescent Vdd-GND current(I_<DDQ>) of a defect-free CMOS circuit is usually very small while a defective circuit often draws excessive I_<DDQ>. As a result, I_<DDQ> information is useful in testing and failure analysis of CMOS circuits. Moreover, it has been shown that the stuck-at fault model and logic testing can not cover some sefects in a CMOS circuit. Thus, I_<DDQ> information is also indispensable in performing high-quality testing and highly efficient failure analysis. This paper uses the transistor short fault model and describes the principle of I_<DDQ> testing, methods of selecting I_<DDQ> test vectors and ways of conducting fault diagnosis with both I_<DDQ> and logic information.

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Recent Trends in Yield Management and Failure Analysis

Tohru Tsujide

Article type: Article
1997 Volume 19 Issue 4 Pages 318-324
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_318

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[title in Japanese]

Article type: Appendix
1997 Volume 19 Issue 4 Pages 325-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_325

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[title in Japanese]

Article type: Appendix
1997 Volume 19 Issue 4 Pages App1-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_App1

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[title in Japanese]

Article type: Cover
1997 Volume 19 Issue 4 Pages Cover2-
Published: June 10, 1997
Released on J-STAGE: March 02, 2018

DOIhttps://doi.org/10.11348/reajshinrai.19.4_Cover2

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