抄録
Described herein is a Data Reduction System which is all transistorized and consists of a input output part, a central processor of stored-program type and a drum memory. Input signals (0-5V) from the transducers of electronic controllers are switched by reed relays at the rate of 30 msec per point. Addresses up to 512 are provided in the memory for storing the original process data, which are digitized by AD/DA converter of 0.1% accuracy. Digital input signals including on-off switch signals can also be accepted. The totalizing circuit to accumulate digital signals of electric power, flow, etc. up to 128 points is useful to eliminate the totalizer in instrumentation. The system has analog and digital output. Output signals (0-5V) are given to the electronic controllers' set-points for opti num process control. Controllers up to 128 can be connected with the system. Digital output are log sheets by the type-writers, on-off control signals and digital informations sent to other digital equipment.
Brief specifications of the central processor are as follows: 24 bits word including sign bit; fixed point and fractional expression; stored program; 1+11/2 address; 23 basic instructions; addition and sub traction time 1.10 msec; multiplication time 4.53 msec; division time 4.85 msec: maximum memory capa city 32 000 words on the drum.
The systen design for reliability, cost down and high speed operation of the syste n is described first. Second is input-output part. Third, the description on the central processor includes the state-counter controlling the operation, usage of a single flip-flop for many purposes, execution time and non-restoring method in division, and switches used for protection of stored-program from noise disturbance. One-word register on the dru n and read/write amplifier of non-return-to-zero method are described in the chapter of drum memory.
