Architecture of a Field-Programmable VLSI Processor Using Memory-Based Cells

Naotaka Ohsawa; Masanori Hariyama; Michitaka Kameyama

doi:10.11499/sicep.2002.0.406.0

SICE Annual Conference 2002

DOI https://doi.org/10.11499/sicep.2002.0.406.0

会議情報

主催: The Society of Instrument and Control Engineers

共催: IEEE/Industiral Electronic Society, IEEE/Robotics and Automation Society, IEEE/Control System Society

Architecture of a Field-Programmable VLSI Processor Using Memory-Based Cells

Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama

著者情報

キーワード: FPGA, Bit-serial architecture, Two-dimensional mesh network

会議録・要旨集フリー

p. 406

詳細

抄録

This paper presents a field programmable VLSI based on a two-dimensional cell array and bit-serial architecture. Bit-serial architecture achieves high utilized ratio irrespective of the word length. Moreover, based on the regular data flow of bit-serial architecture, a lookup table implemented using a shift register is proposed for the cell. One of the arithmetic/logic, memory and control functions is selected in a cell. As a result, area of the cell is reduced.

責任著者(Corresponding author)

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