SICE Annual Conference Program and Abstracts
SICE Annual Conference 2004
会議情報

Sampling rate conversion by Fourier interpolation
*Manabu InoueFuminori KobayashiMinoru Watanabe
著者情報
キーワード: FPGA, digital audio
会議録・要旨集 フリー

p. 23

詳細
抄録
New time-domain SRC using Fourier interpolation to achieve less gate count than in frequency domain is proposed and implemented by FPGA. Layout area of the proposed SRC based on a 0.35um process is 5.728mm2, smaller than the conventional SRC using filters. The noise level is reduced down to the quantization error level by using several improving methods.
著者関連情報
© 2004 SICE
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