抄録
This paper describes a high frequency PLL (Phase Locked Loop) synthesizer with a function of learning then eliminating repeatable fluctuation of timing intervals on series input pulses. Typical spindle encoder generates digital pulses according to the revolution speed. The intervals of each pulse have repeatable fluctuation every revolution by eccentricity or warpage of the encoder scale disk. This method provides a programmable counter for the loop counter of PLL circuit and an interval counter with memory in order to learn the repeatable fluctuation. After the learning process, the PLL generates very pure tone clock signal based on the real flutter components of the spindle revolution speed without influenced by encoder errors. This method has been applied to a hard disk test system in order to generate 3GHz read/write clock.
