非破壊読出し用パルス幅変調器における記憶保持特性のシミュレーション

抄録

The objective of this study is to simulate the memory holding characteristic of the pulse width modulator (PWM) for nondestructive readout which has been proposed as an analog core memory. This characteristic is represented by the percentage difference of the output pulse width versus the number of readout. It is showed by a saturation curve, and gives a significant clue to a designer of the modulator.
By measuring various hysteresis loops of the two-hole core, it is confirmed that the nature of saturation depends upon the hysteresis phenomenon due to the roundabout flux toward write-in leg during a readout operation. The transfer model of the flux level in PWM is proposed by taking into consideration the flux pattern at every readout and the hysteresis model of partial flux reversal proposed by Harada. The recurrence equations for the output pulse widths are derived from the model, which is based on the assumptions that the slope of the irreversible region declines in proportion to the reversed flux level and that the threshold level changes gradually. The characteristic is calculated by a computer, and then it is confirmed that the model can well express the complicated transfer of the flux in PWM.