計測自動制御学会論文集
Online ISSN : 1883-8189
Print ISSN : 0453-4654
ISSN-L : 0453-4654
高速零位法による最短時間PLL
小林 史典坂本 泰彦中野 道雄
著者情報
ジャーナル フリー

1980 年 16 巻 4 号 p. 573-578

詳細
抄録
A new configuration of phase-lock(ed) loop achieving a peerlessly rapid performance is presented in comparison with the conventional PLL's having limited responsiveness. The principle proposed in this paper makes a step further than an improvement on the existing structure; namely, a time-optimal condition is considered in terms of the input/output relationship regarding the circuit as a black box, and a PLL is devised anew realizing the condition and being free from the traditional arrangement. The outcome PLL features two distinctive properties in operation; i. e., the employment of period rather than frequency as the control variable by the use of a voltageto-period converter, and the replacement of the loop filter by time-discrete elements. A prototype comprising 10 IC's demonstrates that the time-optimal PLL can track in 2 cycles any abrupt frequency shift smaller than 1 octave and it provides an FM demodulation output free of ripples in a frequency range of 0.01Hz to 100kHz.
著者関連情報
© 社団法人 計測自動制御学会
前の記事 次の記事
feedback
Top