抄録
High-speed, low-cost FFT processors have been expected in many signal procesing applications. In this paper, a new architecture of a pipelined FFT processor is proposed to meet higher performance requirements. The processor is an SIMD machine which consists of processing elements (PE's), their interconnection circuit, and a control unit. A multiplier, an adder and memories are used as main components in each PE. One of the most important features in the FFT processor is to realize a pipelining operation so that the operating ratios of the functional elements in PE's become high. Especially, the operating ratio of the multiplier is a key point because it is very cost-effective in signal processing hardware components. In order to get the higher throughput in the multiplier, two RAM's for alternative storing and loading are provided in each memory unit. Thus, the processor can be operated at the highest speed in the FFT processors with the same number of the multipliers. An auto-scaling circuit is also provided to get a higher-precision arithmetic. The 1024-point, 8-bit FFT processor with 11-stage PE's including a windowing stage has been implemented by conventional TTL IC's. The sampling frequency of 2.6MHz and FFT processing time of 0.4msec can be obtained. This performance is superior to those of the other implemented FFT processors and enables many ultra-high-speed signal processing applications.
