Design of Robust-Fault-Tolerant Parallel Arithmetic Circuits

Abstract

The robust-fault-tolerance is a property that a computational result becomes nearly equal to the correct one at the occurrence of a fault on the input and output of any gates. In this paper, a robust-fault-tolerant parallel adder and a multiplier are proposed for highly safe digital system. Special numerical representation called distributed coding is introduced to satisfy robust-fault-tolerance, in which a numerical value is expressed by the number of 1's. The intermediate results of the arithmetic circuits is almost equal to the total number of 1's in the input data. This property makes linearly additive effect with small weight to the final result in the occurrence of both temporary and permanent faults.