制御向き状態空間ディジタルフィルタ用高性能VLSIプロセッサの設計と性能評価

抄録

State-space digital filters can synthesize the optimal filter structure with respect to overall quantization effects, but have many more multiplications than a canonical structure has. Therefore the sampling rate and the latency become important problems on implementing these filters. Especially for the very long latency the control system becomes unstable when these filters are used in the feedback control systems, such as the robot control system.
Previously we proposed a VLSI-oriented highly parallel architecture for state-space digital filters with high sampling rate and small latency. For the purpose of further speeding up and reducing hardware complexity, the distributed arithmetic, of which processing time depends on only word length, was applied to this architecture, making good use of high accuracy of state-space digital filters. Therefore, the very high sampling rate can be implemented independently of the filter order and the numbers of the inputs and outputs.
This paper designs and evaluates high-performance VLSI processor based on our proposed VLSI architecture for state-space digital filters using distributed arithmetic. As a result, we confirm that the processor can perform the sampling rate of about 1.67-MHz and the latency of 600ns using 0.8μm CMOS technology, in the case where the filter order is 16, the numbers of inputs and outputs are 1, respectively, and the word length is 14. Moreover, we show that the high sampling rate of about 1.6-MHz can be held constant, even if the filter order and the numbers of inputs and outputs increase.