ロジックインメモリアーキテクチャに基づく道路抽出用VLSIプロセッサの構成

抄録

New logic-in-memory architecture of a high-performance road-extraction VLSI processor is proposed to solve data transfer bottleneck between a memory and processing elements. A VLSI-oriented algorithm having parallelism and regularity is developed to check whether a car can go through the 3D topographical map obtained from 3D instrumentation. To execute the algorithm very fast based on locally parallel processing, a highly parallel VLSI processor with many redundant processing elements is discussed. The processing element consists of an arithmetic element and a register for the storage of the topographical data. A shift register is constructed in the processing element array, so that data transfer between adjacent registers is effectively done. The topographical data once read out from a memory is being stored in shift registers and it is reused until the related processing is completed, so that memory bandwidth becomes minimum. Allocation such that data transfer bottleneck between processing elements becomes minimum is discussed, and it is made clear that the logic-in-memory architecture based on dynamic active control of the redundant processing elements is very useful for the high-performance parallel processing. Finally, the evaluation of the proposed VLSI processor is done, and its superiority to other equivalent processors is made clear from the viewpoint of performance and hardware complexity.