Implementation of an Ultra-High-Speed Path Planning VLSI Processor Using a ROM-Type Content-Addressable Memory

Abstract

For high-speed collision detection, high-computational power is required in not only matching operation between pixel information of a robot manipulator and obstacles but also coordinate transformation. The proposed VLSI processor consists of content-addressable memories (CAMs) for parallel matching operation and processing elements (PEs) for parallel coordinate transformation. Design optimization can be attributed to minimization of the area-time product of a CAM and a PE under a condition of their 100% utilization. Since pixel information of each manipulator link is predetermined and not changed, a high-performance CAM based on a ROM cell is proposed for area-time-product reduction of a CAM. A PE based on a bit-serial pipelined architecture is also proposed for area-time-product reduction of a PE. A test chip is implemented in the 0.6μm CMOS double-metal technology. Its evaluation shows that the performance of the VLSI processor is three orders of magnitude higher than that of a general-purpose microprocessor.