A System Verification Methodology based on Check-Point Extraction Method

Abstract

Recently, system verification plays an important role in Design of large scale and complex systems, embedded systems, and other critical systems. However, it is very difficult for designers other than the specialist who is well versed in Temporal Logic to specify behaviors of the system. In this paper, we consider where designers of systems can extract check-points, necessary signal events, in model checking of formal verification. Moreover, we demonstrate some specification examples, and some verification results by NuSMV model checking tools.