抄録
This paper investigates the gains and losses in terms of power, area, reliability, and speed when applying time redundancy fault tolerance techniques on single core designs compared to space redundancy fault tolerance techniques applied to multi-core designs. The system is developed on the virtex5 FPGA from Xilinx, it uses 65nm technology with a relatively moderate to high static power consumption. The system consists of two design alternatives. The first is a single core embedded processing system that applies time redundancy fault tolerance through execution repetition to perform self-check pointing through consensus. The second system is built from 3 soft IP core processors which perform a space redundancy approach through Triple-Modular-Redundancy (TMR) with feedback among the processors. The performance of both systems is evaluated in terms of the execution speed and latency due to fault tolerance techniques compared to the non-fault tolerant system.
