FPGA-Accelerated VXLAN Chaining for Partially Reconfigurable VNFs in Heterogeneous Data Centers

抄録

Field-Programmable Gate Arrays (FPGAs), with their parallelism, programmability and Partial Reconfiguration (PR), offer great potential for accelerating heterogeneous data center networks and Virtual Network Functions (VNFs). Virtual Extensible LAN (VXLAN) enables scalable virtualized networks, chaining for multi-tenant VNFs by encapsulating packets in UDP packets. However, software-based solutions like Open vSwitch (OVS) incur CPU overhead, limiting performance. This paper presents an FPGA-accelerated VXLAN chaining prototype for PR VNFs in heterogeneous data centers with a hardware-software co-design based on our previous work, RosebudVirt, which is a high-performance and PR virtualization framework designed for virtualized networks. The hardware implements a line-rate VXLAN packet-processing pipeline, with exact matching (EM) using Cuckoo hashing, longest prefix matching (LPM) based on Content-Addressable Memory (CAM) or Ternary Content-Addressable Memory (TCAM), and linear search, achieving 100 Gbps line rate. The software agent optimizes storage utilization, supports over 1 million tenants, and achieves 99.97% utilization in a 4-slot Cuckoo hashing EM table for VXLAN Tunnel Endpoint (VTEP) mapping. Implemented on the Xilinx Alveo U200 platform, our prototype achieves a 193.67-times throughput improvement and a 99.85% latency reduction compared to OVS, without additional CPU overhead, offering a scalable solution for FPGA-accelerated VXLAN chaining for PR VNFs in multi-tenant heterogeneous data centers.