IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
Pietro NANNIPIERIDaniele DAVALLELuca FANUCCI
著者情報
キーワード: VLSI, 8b10b, parallel, encoding
ジャーナル 認証あり

2018 年 E101.A 巻 7 号 p. 1120-1122

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8B/10B is an encoding technique largely used in different communication protocols, with several advantages such as zero DC bias. In the last years transmission rates have grown rapidly, thus the need of encoders with better performance in terms of throughput, area and power consumption raised rapidly. In this article we will present and discuss the architecture of two symbols parallel encoder, comparing it with a classical pipelined solution.

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© 2018 The Institute of Electronics, Information and Communication Engineers
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