A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding

抄録

Real-time on-chip measurement of bit error rate (BER) for high-speed analog-to-digital converters (ADCs) does not only require expensive multi-port high-speed data acquisition equipment but also enormous post-processing. This paper proposes a low-cost built-in-self-test (BIST) circuit for high-speed ADC BER test. Conventionally, the calculation of BER requires a high-speed adder. The presented method takes the advantages of Gray coding and only needs simple logic circuits for BER evaluation. The prototype of the BIST circuit is fabricated along with a 5-bit high-speed flash ADC in a 90-nm CMOS process. The active area is only 90µm × 70µm and the average power consumption is around 0.3mW at 700MS/s. The measurement of the BIST circuit shows consistent results with the measurement by external data acquisition equipment.