Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders

Kazuhito ITO; Ryoto SHIRASAKA

doi:10.1587/transfun.E96.A.2680

Special Section on VLSI Design and CAD Algorithms

Hardware Efficient and Low Latency Implementations of Look-Ahead ACS Computation for Viterbi Decoders

Kazuhito ITO, Ryoto SHIRASAKA

著者情報

キーワード: Viterbi decoding, convolutional code, look-ahead computation, high throughput

ジャーナル認証あり

2013 年 E96.A 巻 12 号 p. 2680-2688

DOI https://doi.org/10.1587/transfun.E96.A.2680

詳細

抄録

The throughput rate of Viterbi decoding (VD) is not limited by the speed of functional units when look-ahead computation techniques are used. The disadvantages of the look-ahead computation in VD are the hardware complexity and the decode latency. In this paper, implementation methods of the look-ahead ACS computation are proposed to improve the hardware efficiency and reduce the latency where the hardware efficiency and the latency can be balanced with a single parameter.

責任著者(Corresponding author)

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