抄録
The emerging three-dimensional (3D) technology is considered as a promising solution for achieving better performance and easier heterogeneous integration. However, the thermal issue becomes exacerbated primarily due to larger power density and longer heat dissipation paths. The thermal issue would also be critical once FPGAs step into the 3D arena. In this article, we first construct a fine-grained thermal resistive model for 3D FPGAs. We show that merely reducing the total power consumption and/or minimizing the power density in vertical direction is not enough for a thermal-aware 3D FPGA backend (placement and routing) flow. Then, we propose our thermal-aware backend flow named TherWare considering location-based heat balance. In the placement stage, TherWare not only considers power distribution of logic tiles in both lateral and vertical directions but also minimizes the interconnect power. In the routing stage, TherWare concentrates on overall power minimization and evenness of power distribution at the same time. Experimental results show that TherWare can significantly reduce the maximum temperature, the maximum temperature gradient, and the temperature deviation only at the cost of a minor increase in delay and runtime as compared with present arts.
