IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Special Section on VLSI Design and CAD Algorithms
A Test Pattern Compaction Method Using SAT-Based Fault Grouping
Yusuke MATSUNAGA
著者情報
キーワード: ATPG, SAT, test pattern
ジャーナル 認証あり

2016 年 E99.A 巻 12 号 p. 2302-2309

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抄録

This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.

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© 2016 The Institute of Electronics, Information and Communication Engineers
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