An Approach for Hardware Trojan Detection using Triple Modular Redundancy in Approximate Synthesis (HT-TRAPS)

抄録

Approximate computing (AC) has been increasingly used to meet the growing demand for energy-efficient and high-performance computing in error-tolerant applications, particularly in the fields of machine learning, signal processing, and multimedia applications. Approximate synthesis tools are an essential component in approximate circuit design and optimization as they enable designers to trade-off accuracy for reduced power consumption, area, and delay. However, these approximate synthesis tools are quite vulnerable to adversarial attacks as it is quite challenging to distinguish between a change in the functionality of the given circuit due to an approximation or a Hardware Trojan (HT). In this paper, we propose an approach for HT detection using Triple modular Redundancy in APproximate Synthesis (HT-TRAPS) tools. The approach also utilizes functional and side channel power and timing analysis to distinguish approximations from HTs and is applicable for either identifying a clean netlist or detecting the presence of a HT at the gate-level post-approximate synthesis stage. We implement the HT-TRAPS approach using a full stack of open-source and commercial tools, including BLASYS, ABACUS, SCOAP and Xilinx Vivado, and thoroughly evaluate its effectiveness by detecting various Trojan benchmarks, such as B19-T100, B19-T200, and B19-500 Trojans, inserted in several circuits, such as the approximated Absolute Difference calculator, Butterfly filter, a classifier, x2, a 16-bit Multiplier and a 32-bit Adder.