Regular Section
An Optimized Low-Power Optical Memory Access Network for Kilocore Systems
キーワード:
optical network-on-chip,
memory access
2019 年 E102.D 巻 5 号 p. 1085-1088
詳細
2019 年 E102.D 巻 5 号 p. 1085-1088
An optimized low-power optical memory access network is proposed to alleviate the cost of microring resonators (MRs) in kilocore systems, such as the pass-by loss and integration difficulty. Compared with traditional electronic bus interconnect, the proposed network reduces power consumption and latency by 80% to 89% and 21% to 24%. Moreover, the new network decreases the number of MRs by 90.6% without an increase in power consumption and latency when making a comparison with Optical Ring Network-on-Chip (ORNoC).
