Negation-Limited Inverters of Linear Size

抄録

An inverter is a circuit which outputs ¬x₁, ¬x₂, …, ¬x_n for any Boolean inputs x₁, x₂, …, x_n. We consider constructing an inverter with AND gates and OR gates and a few NOT gates. Beals, Nishino and Tanaka have given a construction of an inverter which has size O(nlog n) and depth O(log n) and uses ⌈ log(n+1) ⌉ NOT gates. In this paper we give a construction of an inverter which has size O(n) and depth log^1+o(1)n and uses log^1+o(1)n NOT gates. This is the first negation-limited inverter of linear size using only o(n) NOT gates. We also discuss implications of our construction for negation-limited circuit complexity.